1. Thinking about going USB

    The USB specs are pretty large.

    Specifications

    USB 2.0 specs [1]. Explanations [2].

    Good description of the protocol [3].

    Another source [4].

    Protocol analyzers

    USB communications can be spyed with:

    Software Wireshark (example video there [5]).

    Hardware OpenVizsla An Open-source FPGA-based USB sniffer [6]... based of the Xilinx Spartan ...

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  2. OpenOCD and STM32F446

    OpenOCD does know the STM32F446?

    Open On-Chip Debugger 0.8.0 (2014-05-10-23:20)
    Licensed under GNU GPL v2
    For bug reports, read
            http://openocd.sourceforge.net/doc/doxygen/bugs.html
    Info : This adapter doesn't support configurable speed
    Info : STLINK v2 JTAG v17 API v2 SWIM v0 VID 0x0483 PID ...
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  3. I am on reddit, Woo-Hoo!

    I am trying to motivate me to do this project for months now, and I looked like nobody cared about it.

    Thanks to Google webmaster tools (not Google Analytics, I care about your privacy, dear reader), I was able to see which other site linked my blog. Reddit does it ...

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  4. STM32F4: Generating parallel signals with the FSMC

    The goal: The memory controller can be used to generate a "generic" 16-bit parallel data stream with clock. Address generation will be disregarded, as well as other control signals dedicated to memory chips.

    It must be noted that the STM32F40x and STM32F41x have the FSMC (static memories), while the STM32F42x ...

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  5. Spartan-6 configuration speeds

    Spartan-6 maximum JTAG clock is 18-33MHz according to "Table 3: Maximum JTAG Clock Frequencies" in [DS593] (v1.4, p. 8).

    The Spartan-6 at speed grade -1L is limited to 18MHz, while other speed grades (-2, -3N, and -3) allows a TCK of 33MHz. See "Configuration Switching Characteristics" in [DS162] (v3 ...

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  6. In the morning, everything works

    ...after finding a shortcut on the JTAG adapter board and burning an FPGA by connection the power supply the wrong way, in the morning, everything finally works together.

    Config/program access

    Microcontroller debug. access over SWD. The STM32F4x CPU is found:

    Open On-Chip Debugger 0.8.0 (2014-05-10-23:20)
    Licensed ...
    read more
  7. STM32F4 and OpenOCD with flash erase error -304

    Quick post about OpenOCD and flash erase error -304.

    Getting the following error:

    Open On-Chip Debugger 0.8.0 (2014-05-10-23:20)
    Licensed under GNU GPL v2
    For bug reports, read
            http://openocd.sourceforge.net/doc/doxygen/bugs.html
    Info : This adapter doesn't support configurable speed
    Info : STLINK v2 JTAG ...
    read more
  8. Nothing works!

    Buying a cheap analog multimeter at Conrad [1]... and having to repair it right out of the box!

    The discret wire connecting the battery to the voltmeter line was broken. Fortunately, this analog multimeter is so simple that you can reverse engineer it easily and find the issue.

    References

    [1 ...
    read more
  9. FLRe project overview

    Inside of the FLRe first complete prototype.

    The microcontroller and FPGA boards are inserted facing each other in the (upper and lower) PCB guide grooves of the enclosure.

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  10. Desolder the microcontroller?

    Let's desolder the microcontroller?

    Damn, this is just standard solderwire, nothing to do with the desoldering alloy and its low melting point. Ordering mistake... (u_u)

    Result, went a bit medieval on the poor chip...

    read more
  11. STM32F4 JTAG: first tests

    The FLRe p1 microcontroller board is finished and ready for tests. First test? Trying to get the CPU chip id over JTAG.

    The target board uses a custom 0.5" JTAG header. Some home-made adapter are needed.

    Open On-Chip Debugger 0.8.0 (2014-05-10-23:20)
    Licensed under GNU GPL v2 ...
    read more
  12. STM32F4 bare-metal start-up and real bit banging speed

    Last year, I made a post about the bit-banging capacities of the STM32F1 (ARM Cortex-M3) microcontroller. Here are some comparisons with the STM32F4 (Cortex-M4).

    STM32F4 bare metal start-up (no compiler libraries added)

    The STM32F4 runs at 168MHz CPU clock.

    Because my oscilloscope only goes up to 50MHz, I made a ...

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  13. OpenSTM32 and STM32CubeMX under Ubuntu 14.10

    This post is about using OpenSTM32 plugins for Eclipse and STM32CubeMX with Ubuntu 14.10.

    OpenSTM32

    OpenSTM32 [1] is a project aiming at making embedded development for STM32 microcontroller easier with Eclipse. "System Workbench for STM32 - Bare Metal Edition" features are described at [2]. There is an all-in-one installer for ...

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  14. Breakout board for the Spartan-6 LX4/LX9

    Merci Kevin!

    Kevin Modzelewski made a little breakout board for the Xilinx Spartan-6 in TQG-144 package. He describes his FPGA project here [1], and he gives the Gerber source there [2].

    This simple board is useful to learn about the Spartan-6 and test your soldering skills before starting a more ...

    read more
  15. FLRe: automated LUT test strategy

    Foreach LUT:
     1. generate the LUT bitstream with location constraint.
        -> using command-line Xilinx toolchain
    
     2. upload the bitstream to the FPGA.
        -> using FLRe demo board and JTAG control
    
     3. readback the memory area containing the LUT equation and
        match it with the sent bitstream.
        -> using FLRe demo board and JTAG ...
    read more
  16. Carry my LUT around

    Goal have a look-up table (LUT) generated at a known location and test its equation, while dynamically changing it.

    Generation script for the Xilinx FPGA config using ISE

    Files:
    • myProject_map.ncd (Native Circuit Description)
    • myProject.pcf (constraint file)
    • myProject.ncd (same format, but includes additional place and route information)
    • myProject ...
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  17. Reading from serial line

    Simple example code to read the serial port under GNU/Linux

    This code is expected to do something similar to

    cat /dev/ttyUSB0
    
    /* Reading from serial line
     * written by vjp
     * on 2015.03.12 */
    
    #include <stdio.h>
    #include <sys/types.h>
    #include <sys/stat.h>
    #include <fcntl.h>
    #include <sys ...
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  18. Setup of the FLRe test environment

    The FLRe automated test environment is meant to verify the validity of the FPGA dynamic reconfiguration code for all CLB (configurable logic block) of the Spartan-6 LX9 silicon die.

    The FLRe client is compiled on the Raspberry Pi and sends requests over UART to the demo board, which processes the ...

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  19. FLRe project, KiCAD rendering

    First version of the FLRe system. Introduction time!

    The project is made of two modular boards: one microcontroller board and one FPGA board. Each boad can be used separately (each has its own power stage), but they are designed to work together over the 50MHz 16-bit parallel SelectMAP bus of ...

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  20. Spartan-6 SelectMap port length matching

    Update 2015.03.09 it is quite funny that CERN made a video exactly on the same day (2015.03.03) about KiCAD new features for trace length matching. Thanks CERN! See [1].

    Further experiences with KiCAD, FreeRouting and track length matching.

    FreeRouting has a quite nice support for fixed ...

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  21. Spartan-6 start-up sequence and control from microcontroller

    Before wiring everything on the PCB, let's check the Spartan-6 configuration sequence from microcontroller.

    Power-on

    On power-on, both boards (microcontroller and FPGA) will get power supply, but only the microcontroller chip will start because the power supply rail of the FPGA is controlled by a relay which will be ...

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  22. KiCAD Schematics for XC6SLX9

    Where is the KiCAD schematic component for the Xilinx Spartan-6 LX9 (XC6SLX9-TQFP144)?

    Numato Labs made the Mimas Spartan-6 development board using KiCAD, and this FPGA silicon and package. The KiCAD component can be found in their Subversion repository at [1].

    KiCAD and Omron MOSFET relay G3VM-61G1

    References

    [1]Numato Labs ...
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  23. Dreaming of 0402?

    Dreaming of 0402? They are cute but damn small for handsoldering... or are they?

    Introducing the keyring-shaped 0402 challenge!

    An USB connector... a voltage regulator and its two capacitors... on a 2x2cm PCB... nothing special so far, but if you flip the board...

    ... a SMD soldering challenge!

    To light up ...

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  24. FLRe STM32F4 board (paper)

    FLRe microcontroller paper PCB is ready!

    All capacitors and resistors are in 0805 SMD size.

    The alignment of the pin header footprints don't match with the enclosure constrains. (u_u)

    read more
  25. FLRe STM32F4 board (misc. footprints)

    All the footprints are ready. The boot mode (BOOT0 and BOOT1) will be set via a SMD DIP switch. The different power supplies will be accessible throught 1.27mm-pitch THT pin headers.

    Board layout

    Now finally starts the fun of tidying everything of the board.

    As it can be guessed ...

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  26. FLRe STM32F4 board (part1)

    The schematic of the FLRe STM32F4 microcontroller board has started.

    read more
  27. vjCanUsb (intro)

    Presentation

    vjCanUsb is an USB-to-CAN interface featuring:

    • one STM32F4 ARM Cortex-M4 microcontroller running at 168MHz (192KB RAM, 1MB flash). The Complete datasheet: [DH].
    • two 3.3V LDO linear regulators, one for the digital as well as one dedicated to the analog power supply. USB power is filtered by a ferrite ...
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  28. Product thoughts - Microcontroller board initial layout

    Above: the STM32F40x in its LQFP64 package cannot be used because it lacks FSMC support (unbound silicium pads, see [1] rev.4 p. 59). The LQFP144 poackage has full FSMC support, while the LGFP100 package has limited support: data lines only, and no address lines. Since the address lines will ...

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  29. Product thoughts - SelectMAP bus and additional IO

    Above: Custom footprint for the SelectMAP 20-bit bus interface between the microcontroller board and the FPGA board. The bus is insipired from the configuration architecture as found in [UG380] (v.2.5, p.146). The 16 first pads are the 16-bit parallel data bus, and the 4 last pads are ...

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  30. FLRe front panel

    Just got the PCB of the front panel...

    First experiences with the front panel

    The PCB matches the size of the metal cover of the enclosure with a surprising accuracy, and the result looks quite professional. About the PCB itself, most of the footprints are homemade, and one notices immediatly ...

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  31. Server reboot, first time

    Because of the required update of the glibc [1], I had to reboot the Raspberry Pi running this webserver. Just before it restarted for the first time, I quickly got the uptime of the server:

    The server is runnning fresh since today!

    References

    [1]GNU/Linux Glibc “Ghost” bug, https ...
    read more
  32. Product thoughts - part2

    Dreaming of making a real-life product. Part two.

    I decided to go for a stacked two-PCB design with a front panel also made as a PCB. The Hammond 1455 enclosure is available in 80x50x20mm (approx.) dimensions. If no large components are used on one side of each PCB, two PCBs ...

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  33. Track length matching with KiCAD and FreeRouting

    KiCAD does not support length matching, but there is to achieve some manual length matching using FreeRouting [1]. Unfortunately, FreeRouting has little documentation outside of the official manual [2].The idea comes from this blog post at Numato Labs [3]. Designing a Spartan-6 FPGA board with SDRAM, they needed to ...

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  34. KiCAD and Spartan-6 LX9 TQG144

    How to design a Spartan-6 PCB?

    The Spartan-6 LX9 is available in the hand-soldering-friendly TQG144 package ([UG385] v2.3 at p. 30). Numato designed an open-hardware board around this FPGA/packaging: the Mimas Spartan-6 devel. board [NUM1]. The KiCAD [1] schematics and PCB layout files are found in Numato's ...

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  35. Product thoughts

    Dreaming of making a real-life product.

    PCB prototyping services

    Prices are for one 50x100mm 2-layer (front and back) standard PCB with green soldermask

    • http://www.jackaltac.com 37€ (includes 21% VAT), up to 100x100mm and top silkscreen, min track 0.15mm, min hole 0.3mm, made in South Africa and ...
    read more
  36. FLRe project restarts!

    The FLRe project restarts... with my first coffee machine ever!

    Plan for the next steps: build an automated test system, so as to validate the FLRe source code for each LUT in the Spartan-6 LX9 FPGA. The test system will be supervised by a Raspberry Pi:

    Raspberry Pi -(uart)-> STM32F3 ...
    read more
  37. About fpgatools

    As you may have noticed, the work of this blog is based on the great FpgaTools project [1]. I understood the functionning of the Xilinx Spartan-6 bitstream by reading the source code of this project. The source code is nicely written in plain C-code, but there are not much comments ...

    read more
  38. FLRe contest: win a demo board!

    Announcement

    The FLRe project reaches its first beta version. Let's celebrate and win your own demo board. If you are among the first to answer the question, I will send you a tiny demo board flashed with the demo version of the project... for free! (including the shipping costs ...

    read more
  39. UART flash bootloader and LC-Studio STM32F103C8 board

    $ ./stm32flash -b 115200 -v -w main.hex -g 0x0 /dev/ttyUSB0
    stm32flash 0.3
    
    http://stm32flash.googlecode.com/
    
    Using Parser : Intel HEX
    Serial Config: 115200 8E1
    This bootloader returns 2 extra bytes in PID: 00 41
    Version      : 0x20
    Option 1     : 0x00
    Option 2     : 0x00
    Device ID    : 0x0641 (Medium_Density PL)
    - RAM ...
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  40. First steps with the STM32F4

    Those chip close-ups are always so cute...

    How to start with the STM32F4?

    Of course, the first document to find for any chip is the datasheet [1], and the reference manual [2]. To write the start-up code, the manual of the CPU core [3] will be necessary as well. Then ...

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  41. Spartan6 LX9 to STM32 F4 loop

    The experimental solution with STM32F4 and XC6LX9 discrete development boards.

    This problem is that many pins are hard-wired to some specific features. For example, the SelectMap port cannot be used on my current FPGA board. The goal would be to have 32-bit input and output between the FPGA and the ...

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