FLRe demo howto

First steps

When powering the board up, it will write to the debug console. During start-up, the IDCODE of the FPGA is read and printed to the debug console as well.



If everything works as expected, you should read the following on the debug UART console:
Ready
IDCODE(JTAG): 0x24001093
IDCODE(BITS): 0x24001093
CTL    (BITS): 0x0081
STAT   (BITS): 0x373C
COR1   (BITS): 0x3D00
COR2   (BITS): 0x09EE
BOOTSTS(BITS): 0x0001

Board pinout

Vcc
3V3
3V3

3V3
3V3
Vcc
Not used
PA0
PA1
NST
PD1
NST=not_reset
UART2 (debug):
PA2=RX, PA3=TX
PA2
PA3
PD0
PC15
Not used
Not used
PA4
PA5
PC14
PC13
Not used
PA6
PA7
VABT
PB9
VABT=Vbat
Test signal:
PB0=waiting UART1 data
PB0
PB1
PB8
BT0
BT0=BOOT0
PB2=BOOT1
PB2
PB10
PB7
PB6
Not used
FPGA JTAG:
PB11=TCK, PB12=TMS, PB13=TDO, PB14=TDI
PB12
PB11
PB5
PB4
Microcontroller JTAG:
PA13=JTMS, PA14=JTCK,
PA15=JTDI, PB3=JTDO, PB4=JNTRST
PB14
PB13
PB3
PA15
Not used
PA8
PB15
PA14
PA13
UART1 (control):
PA10=RX, PA9=TX
RX
TX
PA12
PA11
Not used

ground
GND
GND
GND
GND
ground

Test signal

When the board is waiting for requests over UART, the following signal is available on the test signal pin (see pinout).



UART config

For both the control and debug UART interfaces, the link configuration is:
Configuration example with PuTTY:



Do not forget to connect the USB-to-UART adapter to the same ground as the FLRe board, otherwise you will get weird results like this: