I want to create a super fast data trigger on 8-bit words. When the data bus matches the bit pattern, the trigger output is set to high.
module pattern_match( input [7:0] data, input [7:0] match, output trigger ); assign trigger = data == match; endmodule
The corresponding schematic:
And here is the triggering delay: 8ns (2 LUTs in series, each taking 4ns, according to a previous post)
How to make use of the partial reconfiguration capability?
Using partial reconfiguration, the design can be much simpler. There is no need to input the match value.
module pattern_match( input [7:0] data, output trigger ); assign trigger = data == 8'b10101010; endmodule
When hard coding the pattern in the verilog description, this matching system only uses two LUTs: one LUT6 for five of the inputs, and one LUT3 for four inputs (the LUT3 being connected to the LUT6 as one input).
Since the new design still has two layers of LUTs, the trigger delay is the same as before.
If the input bus gets larger, the reconfigurable design allows to save one layer of LUT. Example: for 32-bit data bus, two LUT layers (125MHz), instead of three (83MHz).