1. Breakout board for the Spartan-6 LX4/LX9

    Merci Kevin!

    Kevin Modzelewski made a little breakout board for the Xilinx Spartan-6 in TQG-144 package. He describes his FPGA project here [1], and he gives the Gerber source there [2].

    This simple board is useful to learn about the Spartan-6 and test your soldering skills before starting a more …

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  2. FLRe: automated LUT test strategy

    Foreach LUT:
     1. generate the LUT bitstream with location constraint.
        -> using command-line Xilinx toolchain
    
     2. upload the bitstream to the FPGA.
        -> using FLRe demo board and JTAG control
    
     3. readback the memory area containing the LUT equation and
        match it with the sent bitstream.
        -> using FLRe demo board and JTAG …
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  3. Carry my LUT around

    Goal have a look-up table (LUT) generated at a known location and test its equation, while dynamically changing it.

    Generation script for the Xilinx FPGA config using ISE

    Files:
    • myProject_map.ncd (Native Circuit Description)
    • myProject.pcf (constraint file)
    • myProject.ncd (same format, but includes additional place and route information)
    • myProject …
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  4. Reading from serial line

    Simple example code to read the serial port under GNU/Linux

    This code is expected to do something similar to

    cat /dev/ttyUSB0
    
    /* Reading from serial line
     * written by vjp
     * on 2015.03.12 */
    
    #include <stdio.h>
    #include <sys/types.h>
    #include <sys/stat.h>
    #include <fcntl.h>
    #include <sys …
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  5. Setup of the FLRe test environment

    The FLRe automated test environment is meant to verify the validity of the FPGA dynamic reconfiguration code for all CLB (configurable logic block) of the Spartan-6 LX9 silicon die.

    The FLRe client is compiled on the Raspberry Pi and sends requests over UART to the demo board, which processes the …

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  6. FLRe project, KiCAD rendering

    First version of the FLRe system. Introduction time!

    The project is made of two modular boards: one microcontroller board and one FPGA board. Each boad can be used separately (each has its own power stage), but they are designed to work together over the 50MHz 16-bit parallel SelectMAP bus of …

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  7. Spartan-6 SelectMap port length matching

    Update 2015.03.09 it is quite funny that CERN made a video exactly on the same day (2015.03.03) about KiCAD new features for trace length matching. Thanks CERN! See [1].

    Further experiences with KiCAD, FreeRouting and track length matching.

    FreeRouting has a quite nice support for fixed …

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  8. Spartan-6 start-up sequence and control from microcontroller

    Before wiring everything on the PCB, let's check the Spartan-6 configuration sequence from microcontroller.

    Power-on

    On power-on, both boards (microcontroller and FPGA) will get power supply, but only the microcontroller chip will start because the power supply rail of the FPGA is controlled by a relay which will be open …

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  9. KiCAD Schematics for XC6SLX9

    Where is the KiCAD schematic component for the Xilinx Spartan-6 LX9 (XC6SLX9-TQFP144)?

    Numato Labs made the Mimas Spartan-6 development board using KiCAD, and this FPGA silicon and package. The KiCAD component can be found in their Subversion repository at [1].

    KiCAD and Omron MOSFET relay G3VM-61G1

    References

    [1]Numato Labs …
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  10. Dreaming of 0402?

    Dreaming of 0402? They are cute but damn small for handsoldering... or are they?

    Introducing the keyring-shaped 0402 challenge!

    An USB connector... a voltage regulator and its two capacitors... on a 2x2cm PCB... nothing special so far, but if you flip the board...

    ... a SMD soldering challenge!

    To light up …

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  11. FLRe STM32F4 board (paper)

    FLRe microcontroller paper PCB is ready!

    All capacitors and resistors are in 0805 SMD size.

    The alignment of the pin header footprints don't match with the enclosure constrains. (u_u)

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  12. FLRe STM32F4 board (misc. footprints)

    All the footprints are ready. The boot mode (BOOT0 and BOOT1) will be set via a SMD DIP switch. The different power supplies will be accessible throught 1.27mm-pitch THT pin headers.

    Board layout

    Now finally starts the fun of tidying everything of the board.

    As it can be guessed …

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  13. FLRe STM32F4 board (part1)

    The schematic of the FLRe STM32F4 microcontroller board has started.

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  14. vjCanUsb (intro)

    Presentation

    vjCanUsb is an USB-to-CAN interface featuring:

    • one STM32F4 ARM Cortex-M4 microcontroller running at 168MHz (192KB RAM, 1MB flash). The Complete datasheet: [DH].
    • two 3.3V LDO linear regulators, one for the digital as well as one dedicated to the analog power supply. USB power is filtered by a ferrite …
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  15. Product thoughts - Microcontroller board initial layout

    Above: the STM32F40x in its LQFP64 package cannot be used because it lacks FSMC support (unbound silicium pads, see [1] rev.4 p. 59). The LQFP144 poackage has full FSMC support, while the LGFP100 package has limited support: data lines only, and no address lines. Since the address lines will …

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  16. FLRe front panel

    Just got the PCB of the front panel...

    First experiences with the front panel

    The PCB matches the size of the metal cover of the enclosure with a surprising accuracy, and the result looks quite professional. About the PCB itself, most of the footprints are homemade, and one notices immediatly …

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  17. Server reboot, first time

    Because of the required update of the glibc [1], I had to reboot the Raspberry Pi running this webserver. Just before it restarted for the first time, I quickly got the uptime of the server:

    The server is runnning fresh since today!

    References

    [1]GNU/Linux Glibc “Ghost” bug, https …
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  18. Product thoughts - part2

    Dreaming of making a real-life product. Part two.

    I decided to go for a stacked two-PCB design with a front panel also made as a PCB. The Hammond 1455 enclosure is available in 80x50x20mm (approx.) dimensions. If no large components are used on one side of each PCB, two PCBs …

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  19. Track length matching with KiCAD and FreeRouting

    KiCAD does not support length matching, but there is to achieve some manual length matching using FreeRouting [1]. Unfortunately, FreeRouting has little documentation outside of the official manual [2].The idea comes from this blog post at Numato Labs [3]. Designing a Spartan-6 FPGA board with SDRAM, they needed to …

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  20. KiCAD and Spartan-6 LX9 TQG144

    How to design a Spartan-6 PCB?

    The Spartan-6 LX9 is available in the hand-soldering-friendly TQG144 package ([UG385] v2.3 at p. 30). Numato designed an open-hardware board around this FPGA/packaging: the Mimas Spartan-6 devel. board [NUM1]. The KiCAD [1] schematics and PCB layout files are found in Numato's SVN …

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  21. Product thoughts

    Dreaming of making a real-life product.

    PCB prototyping services

    Prices are for one 50x100mm 2-layer (front and back) standard PCB with green soldermask

    • http://www.jackaltac.com 37€ (includes 21% VAT), up to 100x100mm and top silkscreen, min track 0.15mm, min hole 0.3mm, made in South Africa and …
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  22. FLRe project restarts!

    The FLRe project restarts... with my first coffee machine ever!

    Plan for the next steps: build an automated test system, so as to validate the FLRe source code for each LUT in the Spartan-6 LX9 FPGA. The test system will be supervised by a Raspberry Pi:

    Raspberry Pi -(uart)-> STM32F3 …
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  23. About fpgatools

    As you may have noticed, the work of this blog is based on the great FpgaTools project [1]. I understood the functionning of the Xilinx Spartan-6 bitstream by reading the source code of this project. The source code is nicely written in plain C-code, but there are not much comments …

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  24. FLRe contest: win a demo board!

    Announcement

    The FLRe project reaches its first beta version. Let's celebrate and win your own demo board. If you are among the first to answer the question, I will send you a tiny demo board flashed with the demo version of the project... for free! (including the shipping costs)

    See …

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  25. UART flash bootloader and LC-Studio STM32F103C8 board

    $ ./stm32flash -b 115200 -v -w main.hex -g 0x0 /dev/ttyUSB0
    stm32flash 0.3
    
    http://stm32flash.googlecode.com/
    
    Using Parser : Intel HEX
    Serial Config: 115200 8E1
    This bootloader returns 2 extra bytes in PID: 00 41
    Version      : 0x20
    Option 1     : 0x00
    Option 2     : 0x00
    Device ID    : 0x0641 (Medium_Density PL)
    - RAM …
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  26. First steps with the STM32F4

    Those chip close-ups are always so cute...

    How to start with the STM32F4?

    Of course, the first document to find for any chip is the datasheet [1], and the reference manual [2]. To write the start-up code, the manual of the CPU core [3] will be necessary as well. Then …

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  27. Spartan6 LX9 to STM32 F4 loop

    The experimental solution with STM32F4 and XC6LX9 discrete development boards.

    This problem is that many pins are hard-wired to some specific features. For example, the SelectMap port cannot be used on my current FPGA board. The goal would be to have 32-bit input and output between the FPGA and the …

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  28. Proposal for a dynamic and compact state machine on Spantan-6

    My proposal for an ultra compact 4-bit FSM fitting in one Spartan-6 CLB only, by using dynamic reconfiguration. The overall state machine being itself dynamically reconfigured, allowing to create or remove states, or change transitions or state output...

    Important limitation: so as to make it fit in one CLB only …

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  29. Spartan-6 dynamic reconfiguration summary

    The internal configuration of most of the FPGA currently available (such as the Xilinx Spartan-6) are SRAM-based. Since those configuration bits are directly used by the internal blocks of the FPGA, their behavior is changed right after changing the corresponding bits in the SRAM configuration.

    In my previous posts, I …

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  30. How to read an .ncd file

    The Xilinx design work flow, as described in [1]:

    By the way, it seems that the Debit project is no more available at the address given in the document, but the source code repository can still be found at [2].

    The .ncd file is the most important file, which contains …

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  31. Spartan6 Slice M dynamic reconfiguration

    In my previous post, I documented the configuration options available in the bitstream for the Slice M logic blocks. In order to check whether they are dynamically reconfigurable or not, I experimented with the OUTMUX multiplexer.

    When D5Q ① is selected by OUTMUX, the output DMUX is registered, when O5 …

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  32. Spartan6 Slice M configuration

    The generic building block to make a FPGA is the logic block, which is composed of look-up table and flip-flop. Each FPGA maker has its own design and terms for those Logic Element:

    • Xilinx Spartan 6: Slice M, L, or X with 4 LUT (6 inputs) and 8 Flip-flops, packed …
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  33. Xilinx ISE: preventing registers in IOB

    When creating a design with a registered output, the D Flip-Flop of the final output (just before the FPGA pads) are moved to IOB blocks. See [1]

    Note: Do not try to move the D Flip-Flop to another location in PlanAhead, the tool will behave fine, but will not save …

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  34. High speed serial bus generation using Spartan-6

    My goal is to generate an 8-bit serial data signal and its clock (similar to SPI bus). High-speed serialization can be achieved using SerDes (Serializer Deserializer) dedicated logic in Xilinx Spartan-6 FPGA.

    This post is entirely based on the Xilinx application note [XAPP1064]. General clock configurations are also described in …

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  35. High speed serial trigger using Spartan-6 (improved)

    Implementation of a 8-bit shift register with automatic clear

    module shift_reg(
            clk,
            clear,
            shift_in,
            d_out
            );
    
    input                   clk;
    input                   clear;
    input                   shift_in;
    output [7:0]    d_out;
    reg    [7:0]    d_out;
    reg    [7:0]    count;  // "One Hot" encoding of the current register load
    reg                             reset;  // if 1, register is cleared at next …
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  36. High speed serial trigger using Spartan-6

    The serial trigger includes a shift register and a comparator. When the content of the register matches the expected pattern, the trigger output is set to high.

    First, how to create a simple 8-bit shift register in verilog?

    Implementation of a simple 8-bit shift register

    module shift_reg(
            clk,            // clock
            clear …
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  37. No, computer science is not based on mathematics

    I have heard this sentence quite many times:

    Vincent: "I studied computer science..."

    Someone: "Oh! You must be good in mathematics then!"

    No! There is no need of mathematics to design a computer. Maybe this misconception comes from the English word computer itself, which is based on compute meaning calculate …

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  38. Readback the Spartan-6 configuration registers over JTAG

    Since long time, I failed reading back data from the Spartan-6 configuration registers (STAT, COR1, COR2), even though the sequence is described in the Configuration Register Read Procedure (JTAG) section [UG380] (p.117, v2.5).

    This part contains several incoherencies which led me not to follow each step blindly. Actually …

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  39. Reconfiguration of the trigger pattern

    After having found the location of the LUT in the FPGA die, their equations can be reconfigured.

    Example requests

    [FLR] requests:

    FLR_SID_READ_TARGET
    [TX8]0x0002000000000000
    [RX8]0x0082005555555555
    FLR_SID_SET_LUT_EQU
    [TX8]0x0121030f02050000
    [TX8]0xffffffffffffcccc
    [RX8]0x00a1005555555555
    FLR_SID_SET_LUT_EQU
    [TX8]0x0121030f02060000
    [TX8]0xfffffffffffffffe
    [RX8]0x00a1005555555555
    FLR_SID_WRITE_TARGET
    [TX8]0x0003000100020000
    [RX8]0x0083005555555555
    FLR_SID_WRITE_TARGET
    [TX8]0x0003000400020000
    [RX8]0x0083005555555555 …
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  40. Where is my LUT (in the Spartan-6 LX9)?

    You created your Verilog or VHDL design, and you want to create a placement constraint of some blocks that you plan to reconfigure later during runtime? The live reconfiguration server will need the bitstream coordinates to find those corresponding blocks in the internal FPGA configuration. Unfortunately, the (X, Y) from …

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