Merci Kevin!
Kevin Modzelewski made a little breakout board for the Xilinx Spartan-6 in TQG-144 package. He describes his FPGA project here [1], and he gives the Gerber source there [2].
This simple board is useful to learn about the Spartan-6 and test your soldering skills before starting a more …
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Foreach LUT:
1. generate the LUT bitstream with location constraint.
-> using command-line Xilinx toolchain
2. upload the bitstream to the FPGA.
-> using FLRe demo board and JTAG control
3. readback the memory area containing the LUT equation and
match it with the sent bitstream.
-> using FLRe demo board and JTAG …
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Goal have a look-up table (LUT) generated at a known location and test its equation, while dynamically changing it.
Simple example code to read the serial port under GNU/Linux
This code is expected to do something similar to
cat /dev/ttyUSB0
/* Reading from serial line
* written by vjp
* on 2015.03.12 */
#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <sys …The FLRe automated test environment is meant to verify the validity of the FPGA dynamic reconfiguration code for all CLB (configurable logic block) of the Spartan-6 LX9 silicon die.
The FLRe client is compiled on the Raspberry Pi and sends requests over UART to the demo board, which processes the …
read moreFirst version of the FLRe system. Introduction time!
The project is made of two modular boards: one microcontroller board and one FPGA board. Each boad can be used separately (each has its own power stage), but they are designed to work together over the 50MHz 16-bit parallel SelectMAP bus of …
read moreBefore wiring everything on the PCB, let's check the Spartan-6 configuration sequence from microcontroller.
On power-on, both boards (microcontroller and FPGA) will get power supply, but only the microcontroller chip will start because the power supply rail of the FPGA is controlled by a relay which will be open …
Where is the KiCAD schematic component for the Xilinx Spartan-6 LX9 (XC6SLX9-TQFP144)?
Numato Labs made the Mimas Spartan-6 development board using KiCAD, and this FPGA silicon and package. The KiCAD component can be found in their Subversion repository at [1].
| [1] | Numato Labs … |
Dreaming of 0402? They are cute but damn small for handsoldering... or are they?
An USB connector... a voltage regulator and its two capacitors... on a 2x2cm PCB... nothing special so far, but if you flip the board...
... a SMD soldering challenge!
To light up …
Before starting a PCB design with the Xilinx Spartan-6, the most important document to read is [UG393] and [UG394].
Above: Required PCB Capacitor for the Spartan-6 LX9, [UG393] (v1.3, p. 14).
I discovered by reading this document, that ([UG393] v1.3, p. 22):
Capacitor package dimensions (body …
FLRe microcontroller paper PCB is ready!
All capacitors and resistors are in 0805 SMD size.
The alignment of the pin header footprints don't match with the enclosure constrains. (u_u)
read moreAll the footprints are ready. The boot mode (BOOT0 and BOOT1) will be set via a SMD DIP switch. The different power supplies will be accessible throught 1.27mm-pitch THT pin headers.
Now finally starts the fun of tidying everything of the board.
As it can be guessed …
The schematic of the FLRe STM32F4 microcontroller board has started.
An alternate supplier: http://uk.farnell.com/samtec/fts-110-01-f-dv/connector-header-1-27mm-smt-20way/dp/2308522 http://www.farnell.com/datasheets/1902580.pdf
Framatome Connectors International (FCI) http://uk.farnell.com/fci/20021121-00006c4lf/header-vert-1-27mm-smt-6way/dp/1865277 (faisait partie d'Areva, vendu 2005)
vjCanUsb is an USB-to-CAN interface featuring:
- one STM32F4 ARM Cortex-M4 microcontroller running at 168MHz (192KB RAM, 1MB flash). The Complete datasheet: [DH].
- two 3.3V LDO linear regulators, one for the digital as well as one dedicated to the analog power supply. USB power is filtered by a ferrite …
Little training before starting the PCB of the FLRe microcontroller board.
This shopping list refers to the following schematic: [1].
- 60.4R (~60R) VISHAY CRCW080560R4FKTABC
- 10kR VISHAY CRCW080510K0FKTABC
- 470R VISHAY CRCW0805470RFKTABC
- 22R VISHAY CRCW080522R0FKTABC
Above: the STM32F40x in its LQFP64 package cannot be used because it lacks FSMC support (unbound silicium pads, see [1] rev.4 p. 59). The LQFP144 poackage has full FSMC support, while the LGFP100 package has limited support: data lines only, and no address lines. Since the address lines will …
read moreJust got the PCB of the front panel...
The PCB matches the size of the metal cover of the enclosure with a surprising accuracy, and the result looks quite professional. About the PCB itself, most of the footprints are homemade, and one notices immediatly …
Dreaming of making a real-life product. Part two.
I decided to go for a stacked two-PCB design with a front panel also made as a PCB. The Hammond 1455 enclosure is available in 80x50x20mm (approx.) dimensions. If no large components are used on one side of each PCB, two PCBs …
read moreKiCAD does not support length matching, but there is to achieve some manual length matching using FreeRouting [1]. Unfortunately, FreeRouting has little documentation outside of the official manual [2].The idea comes from this blog post at Numato Labs [3]. Designing a Spartan-6 FPGA board with SDRAM, they needed to …
read moreThe Spartan-6 LX9 is available in the hand-soldering-friendly TQG144 package ([UG385] v2.3 at p. 30). Numato designed an open-hardware board around this FPGA/packaging: the Mimas Spartan-6 devel. board [NUM1]. The KiCAD [1] schematics and PCB layout files are found in Numato's SVN …
Dreaming of making a real-life product.
Prices are for one 50x100mm 2-layer (front and back) standard PCB with green soldermask
- http://www.jackaltac.com 37€ (includes 21% VAT), up to 100x100mm and top silkscreen, min track 0.15mm, min hole 0.3mm, made in South Africa and …
The FLRe project restarts... with my first coffee machine ever!
Plan for the next steps: build an automated test system, so as to validate the FLRe source code for each LUT in the Spartan-6 LX9 FPGA. The test system will be supervised by a Raspberry Pi:
Raspberry Pi -(uart)-> STM32F3 …read more
Want to change the LUT equation directly in the bitstream of the Xilinx Spartan6 LX9 (XC6SLX9)?
Go to this link for the online converter based on the source code of the FLRe project: https://vjordan.info/cgi/lut_equ_conv
https://vjordan.info/cgi/lut_equ_conv?0011223344550580f0f0f0f000000000
for the native Xilinx bitstream …
The FLRe project reaches its first beta version. Let's celebrate and win your own demo board. If you are among the first to answer the question, I will send you a tiny demo board flashed with the demo version of the project... for free! (including the shipping costs)
See …
$ ./stm32flash -b 115200 -v -w main.hex -g 0x0 /dev/ttyUSB0 stm32flash 0.3 http://stm32flash.googlecode.com/ Using Parser : Intel HEX Serial Config: 115200 8E1 This bootloader returns 2 extra bytes in PID: 00 41 Version : 0x20 Option 1 : 0x00 Option 2 : 0x00 Device ID : 0x0641 (Medium_Density PL) - RAM …read more
Not impressed by the new iPhone6? Looking for a real revolution? (^_^)
See the full pinout here: https://vjordan.info/flr/demo_board/pinout.html
read moreAfter the previous post about how to implement a tiny sate machine in one CLB only?, the point of view of the Spartan-6 silicium die can now be shifted from a sea of logical blocks (CLB), into a sea of potential state machines.
Here is my design proposal for a …
read moreThe experimental solution with STM32F4 and XC6LX9 discrete development boards.
This problem is that many pins are hard-wired to some specific features. For example, the SelectMap port cannot be used on my current FPGA board. The goal would be to have 32-bit input and output between the FPGA and the …
read moreUpdate 2015.05.06 I did the same tests again, and got better results. The reset vector missed this attribute so as to enable compiler opimizations
__attribute__ ((used))
I also added more information about the compiler version [1], the compiler flags [2] used for the tests, and the result according …
read moreThis is the implementation of the 4-state FSM fitting in one configurable logic block (CLB) only, as described in the previous post. The verilog code uses "Device Primitive Instanciation" as documented in [UG615]. Each instance was constrained in the same CLB (2 slices) using BEL and LOC constraints.
Screenshot of …
read moreMy proposal for an ultra compact 4-bit FSM fitting in one Spartan-6 CLB only, by using dynamic reconfiguration. The overall state machine being itself dynamically reconfigured, allowing to create or remove states, or change transitions or state output...
Important limitation: so as to make it fit in one CLB only …
read moreThe internal configuration of most of the FPGA currently available (such as the Xilinx Spartan-6) are SRAM-based. Since those configuration bits are directly used by the internal blocks of the FPGA, their behavior is changed right after changing the corresponding bits in the SRAM configuration.
In my previous posts, I …
read moreIn my previous post, I documented the configuration options available in the bitstream for the Slice M logic blocks. In order to check whether they are dynamically reconfigurable or not, I experimented with the OUTMUX multiplexer.
When D5Q ① is selected by OUTMUX, the output DMUX is registered, when O5 …
read moreThe generic building block to make a FPGA is the logic block, which is composed of look-up table and flip-flop. Each FPGA maker has its own design and terms for those Logic Element:
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- Xilinx Spartan 6: Slice M, L, or X with 4 LUT (6 inputs) and 8 Flip-flops, packed …
My goal is to generate an 8-bit serial data signal and its clock (similar to SPI bus). High-speed serialization can be achieved using SerDes (Serializer Deserializer) dedicated logic in Xilinx Spartan-6 FPGA.
This post is entirely based on the Xilinx application note [XAPP1064]. General clock configurations are also described in …
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module shift_reg(
clk,
clear,
shift_in,
d_out
);
input clk;
input clear;
input shift_in;
output [7:0] d_out;
reg [7:0] d_out;
reg [7:0] count; // "One Hot" encoding of the current register load
reg reset; // if 1, register is cleared at next …The serial trigger includes a shift register and a comparator. When the content of the register matches the expected pattern, the trigger output is set to high.
First, how to create a simple 8-bit shift register in verilog?
module shift_reg(
clk, // clock
clear …I have heard this sentence quite many times:
Vincent: "I studied computer science..."
Someone: "Oh! You must be good in mathematics then!"
No! There is no need of mathematics to design a computer. Maybe this misconception comes from the English word computer itself, which is based on compute meaning calculate …
read moreMany articles already exists about dynamic partial reconfiguration, but they often make use of pre-generated bitstreams (using Xilinx proprietary design suite [1]). Thanks to the amazing work of the guys at fpgatools [2] who reversed engineered most of the internal bits configuration of the Xilinx Spartan6 …
Since long time, I failed reading back data from the Spartan-6 configuration registers (STAT, COR1, COR2), even though the sequence is described in the Configuration Register Read Procedure (JTAG) section [UG380] (p.117, v2.5).
This part contains several incoherencies which led me not to follow each step blindly. Actually …
read moreAfter having found the location of the LUT in the FPGA die, their equations can be reconfigured.
[FLR] requests:
FLR_SID_READ_TARGET [TX8]0x0002000000000000 [RX8]0x0082005555555555 FLR_SID_SET_LUT_EQU [TX8]0x0121030f02050000 [TX8]0xffffffffffffcccc [RX8]0x00a1005555555555 FLR_SID_SET_LUT_EQU [TX8]0x0121030f02060000 [TX8]0xfffffffffffffffe [RX8]0x00a1005555555555 FLR_SID_WRITE_TARGET [TX8]0x0003000100020000 [RX8]0x0083005555555555 FLR_SID_WRITE_TARGET [TX8]0x0003000400020000 [RX8]0x0083005555555555 …
You created your Verilog or VHDL design, and you want to create a placement constraint of some blocks that you plan to reconfigure later during runtime? The live reconfiguration server will need the bitstream coordinates to find those corresponding blocks in the internal FPGA configuration. Unfortunately, the (X, Y) from …
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