Today I analyzed the Xilinx documentation about the bitstream format in [UG380] p.92 (v2.5), and I updated the C code converting bitstream into a C array for generating C comments at each configuration word.
See the full file here: simple_and.c (~4MB) 
All instructions are documented by Xilinx... until a huge write instruction of 170,157 16-bit words: the actual FPGA internal raw configuration frames! (^_^)
Now comes the reverse engineering part... which has fortunately already been done for the Spartan-6 LX9 in the amazing FpgaTools  project.
From Advanced Partial Run-time Reconfiguration on Spartan-6 FPGAs , a research paper about runtime reconfiguration:
The size of a frame is always 130 Byte and carries mainly the configuration for the primitives (e.g., 8 bytes per CLB). It requires to write 31 (23/24) frames to the device for configuring all logic and routing information of one CLB (DSP48/BRAM) primitive.
Unfortunately, this paper does not explain further the encoding of the bitstream itself, neither it modifies it on the fly. Bitstream chunks are pre-generated beforehand.
|[UG380]||Spartan-6 FPGA Configuration User Guide http://www.xilinx.com/support/documentation/user_guides/ug380.pdf|
|||Analyzed simple and configuration simple_and.c|