Goal have a look-up table (LUT) generated at a known location and test its equation, while dynamically changing it.
Generation script for the Xilinx FPGA config using ISE
- Files:
- myProject_map.ncd (Native Circuit Description)
- myProject.pcf (constraint file)
- myProject.ncd (same format, but includes additional place and route information)
- myProject.bit (bitstream)

par -w -intstyle ise -ol high -mt off myProject_map.ncd myProject.ncd myProject.pcf bitgen -intstyle ise -f myProject.ut myProject.ncd
Xilinx Software Design Flow (FPGAs) (see [UG628] v14.7, p. 17)
Xilinx LUT input optimization
The following command will generate an ASCII-version of the .ncd binary file.
xdl -ncd2xdl myProject.ncd
The LUT equation is found in the output file as a string. Example:
O5=((~A2*((~A5*(A3*A4))+(A5*(~A3*~A4))))+(A2*(A5+(A3@A4))))
...but this equation is probably different from the expected equation as configured in ISE, because the switch box to the interconnection matrix might not directly match the input lines of the LUT.

In this sreenshot:
IO_A1 -> LUT_A3 IO_A2 -> LUT_A1 IO_A3 -> LUT_A2 IO_A4 -> LUT_A6 IO_A5 -> LUT_A4 IO_A6 -> LUT_A5
References
[UG628] | Xilinx, Command Line Tools User Guide, http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/devref.pdf |
[1] | Christian Beckhof, The Xilinx Design Language (XDL): Tutorial and Use Cases, http://www.mn.uio.no/ifi/english/research/projects/cosrecos/publications/paper/recosoc11beckhoff.pdf |