Foreach LUT:
 1. generate the LUT bitstream with location constraint.
    -> using command-line Xilinx toolchain

 2. upload the bitstream to the FPGA.
    -> using FLRe demo board and JTAG control

 3. readback the memory area containing the LUT equation and
    match it with the sent bitstream.
    -> using FLRe demo board and JTAG

 4. find the input order of the LUT (automatically optimized
    by Xilinx tool) by testing each input indivitually.
    -> using FLRe dynamic reconfiguration and test I/O of
       the demo board

 5. test a set of equations combining all the inputs.
    -> using FLRe dynamic reconfiguration and test I/O of
       the demo board

Individual pin equations are:

#define LUT_EQU_A1      0xAAAAAAAAAAAAAAAAUL
#define LUT_EQU_A2      0xCCCCCCCCCCCCCCCCUL
#define LUT_EQU_A3      0xF0F0F0F0F0F0F0F0UL
#define LUT_EQU_A4      0xFF00FF00FF00FF00UL
#define LUT_EQU_A5      0xFFFF0000FFFF0000UL
#define LUT_EQU_A6      0xFFFFFFFF00000000UL