First version of the FLRe system. Introduction time!
The project is made of two modular boards: one microcontroller board and one FPGA board. Each boad can be used separately (each has its own power stage), but they are designed to work together over the 50MHz 16-bit parallel SelectMAP bus of the Xilinx FPGA (several FPGA boards can be chained on the same bus).
Xilinx Spartan-6 FPGA board
The PCB is 7.00 x 5.00cm to fit the selected enclosure, but the actual circuit is smaller than expected. Port A, B, and C are general purpose IO, with A and B having been selected at the top of the silicon die (bank 0), to ease dynamic reconfiguration, because logic blocks (CLBs) are organized vertically in the chip. Bottom GPIO were not available since they conflict with the SelectMAP bus (bank 2).
The confiuration mode (M0 and M1) is set with a DIP switch, but it should be noted that the only wired mode is SelectMAP slave (or master). Other settings will require modifications on the PCB.
A solid state relay enables automated hard resets.
Selected chip package is the handsoldering-friendly TQFP-144. Chip power supplies are 1.2V and 3.3V. Other supplies are still easy to hack on the GPIO banks with the help of 0Ω SMD resistors (R6 for bank 0, R7 for bank 1, R8 for bank 2 and R9 for bank 3).
STM32F4 Microcontroller board
The PCB is 6.00 x 5.00cm to fit the selected enclosure. There is an indent of 1cm compared to the FPGA board so as to avoid pin header facing each other when the boards are stacked.
A second LDO voltage regulator supplies the ADC block of the microcontroller.
Two chip packages are supported: TQFP-100 and TQFP-144.