FPGA Live Reconfiguration server

The FPGA Live Reconfiguration server running on a microcontroller takes requests over serial line and apply them to the FPGA target.

The specification of the FLR protocol is here: https://vjordan.info/flr/

The purpose of this project is to allow easy-to-understand FPGA live reconfiguration by hiding the obfuscated bitstream encoding from Xilinx.

Example

1. FRS_SID_READ_TARGET
[TX8]0x0002000000000000
[RX8]0x0082005555555555
2. FRS_SID_SET_LUT_EQU
[TX8]0x0121000d0d050000
[TX8]0x0f0f0f0ff0f0f0f0
[RX8]0x00a1005555555555
3. FRS_SID_WRITE_TARGET
[TX8]0x0003000d0d050000
[RX8]0x0083005555555555

Note: this example is based on a preliminary implementation, hence some request parameters are missing or different.

    1. Get a chunk of the bitstream (using the ReadBack feature of the FPGA)
    1. Patch the bitstream chunk (e.g., change LUT equation)
    1. Write back the patched chunk (using Partial reconfiguration feature of the FPGA)