Hello (FPGA) World over STM32!

The following verilog code was implemented using Xilinx ISE toolsuite:

`timescale 1ns / 1ps

module simple_and(
input a1,
input a2,
output a3

assign a3 = a1 & a2;


At the end, the tool generate a bitstream: a binary file containing raw data ready to be uploaded to the FPGA over JTAG (or SPI, EEPROM, etc). I created a simple C tool to dump the initial section, and create a statically initialized array in a C source file.

/* design : simple_and.ncd;UserID=0xFFFFFFFF */
/* part name: 6slx9tqg144 */
/* date : 2014/04/15 */
/* time : 15:26:25 */
const uint8_t bitstream[340604] = {
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaa, 0x99, 0x55, 0x66,
0x30, 0xa1, 0x00, 0x07, 0x20, 0x00, 0x31, 0xa1, 0x03, 0x80,
0x31, 0x41, 0x3d, 0x08, 0x31, 0x61, 0x09, 0xee, 0x31, 0xc2,

This array contains the complete configuration of all the blocks of the Xilinx Spartan-6 LX9 (approx. 332KB), which is mostly zero since the program uses one LUT and three pins only. As a reference, [UG380] (at p. 73) says 2,742,528 bits for the 6SLX9.

[UG380] at p.163 also explains how to upload the bitstream over JTAG:

  1. Load the instruction CFG_IN, and copy the bitstream.
  2. Load the instruction JSTART, and go back to idle state.
  3. Turn on the oscilloscope and test!

The STM32 GPIO control registers have a neat little feature to sync bit generation between pins: bit set and reset register.

for(;;) {
GPIOA->BSRR = GPIO_BSRR_BR0 | GPIO_BSRR_BR1;        /* 00 */
GPIOA->BSRR = GPIO_BSRR_BS0 | GPIO_BSRR_BR1;        /* 01 */
GPIOA->BSRR = GPIO_BSRR_BR0 | GPIO_BSRR_BS1;        /* 10 */
GPIOA->BSRR = GPIO_BSRR_BS0 | GPIO_BSRR_BS1;        /* 11 */

It generates the following 2-bit truth table:

Et voilĂ ! So much fun with an AND gate! (top is the input signal A1, bottom is the output A3)

Now let's see the time it needs for the LUT to update the output according to the input:

4ns response time. It seems consistant with the datasheet [DS162], but I am not sure whether my oscilloscope is still accurate for such short time measurements...

[UG380](1, 2) Spartan-6 FPGA Configuration User Guide http://www.xilinx.com/support/documentation/user_guides/ug380.pdf
[DS162]Spartan-6 FPGA Data Sheet: DC and Switching Characteristics http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf