High speed serial trigger using Spartan-6 (improved)

Implementation of a 8-bit shift register with automatic clear

module shift_reg(
        clk,
        clear,
        shift_in,
        d_out
        );

input                   clk;
input                   clear;
input                   shift_in;
output [7:0]    d_out;
reg    [7:0]    d_out;
reg    [7:0]    count;  // "One Hot" encoding of the current register load
reg                             reset;  // if 1, register is cleared at next clock

initial d_out = 8'b00000000;
initial count = 8'b00000001;
initial reset = 0;

always @(posedge clk) begin
        // update the 'count' register
        if(clear) begin
                count <= 8'b1;
        end else if(count[7]) begin
                count <= 8'b1;
                reset <= 1;
        end else begin
                count <= {count[6:0], 1'b0};
        end

        // update the 'd_out' register
        if(clear) begin
                d_out <= 8'b0;
        end else if(reset) begin
                d_out <= {7'b0, shift_in};
                reset <= 0;
        end else begin
                d_out <= {d_out[6:0], shift_in};
        end
end

The RTL schematic is now much longer. The first part is the shift register for the counter which end up setting the "reset" register used to clear or not the data shift register in the second part.

Higher resolution picture: serial_trigger_improved_RTL.png

Practical usage

The synthesis software of the Xilinx design chain rates this design at more than 600MHz.