How to read an .ncd file

The Xilinx design work flow, as described in [1]:

By the way, it seems that the Debit project is no more available at the address given in the document, but the source code repository can still be found at [2].

The .ncd file is the most important file, which contains the low level configuration, before it gets converted into the bitstream. This Native Circuit Description (NCD) file is "ASCII-encoded" binary, but there is a way to convert it into a plain-text Xilinx Design Language (XDL). See [3] for more details.

xdl -ncd2xdl myNcdFile.ncd

Some XDL content

The XDL file is divided into two big sections: instances (inst), and network (net).

As example, the OUTMUX settings can be found back here: DOUTMUX::D5Q.

inst "out_0" "SLICEM",placed CLEXM_X14Y2 SLICE_X20Y2  ,
  cfg " A5FFSRINIT::SRINIT0 A5LUT:Mmux_in[3]_GND_1_o_mux_13_OUT41:#LUT:O5=((~A2*((~A5*(A3*A4))+(A5*(~A3*~A4))))+(A2*(A5+(A3@A4))))
            _BEL_PROP::A5LUT:BEL:A5LUT A5RAMMODE::#OFF A6LUT::#OFF A6RAMMODE::#OFF
            ACY0::#OFF ADI1MUX::#OFF AFF::#OFF AFFMUX::#OFF AFFSRINIT::#OFF AOUTMUX::A5Q
            AUSED::#OFF B5FFSRINIT::SRINIT0 B5LUT:Mmux_in[3]_GND_1_o_mux_13_OUT31:#LUT:O5=((~A5*(A1*A3))+(A5*(A1+(~A4*~A3))))
            _BEL_PROP::B5LUT:BEL:B5LUT B5RAMMODE::#OFF B6LUT::#OFF B6RAMMODE::#OFF
            BCY0::#OFF BDI1MUX::#OFF BFF::#OFF BFFMUX::#OFF BFFSRINIT::#OFF BOUTMUX::B5Q
            BUSED::#OFF C5FFSRINIT::SRINIT0 C5LUT:Mmux_in[3]_GND_1_o_mux_13_OUT21:#LUT:O5=((~A3*(~A4*(A2*A5)))+(A3*((~A4*~A2)+A5)))
            _BEL_PROP::C5LUT:BEL:C5LUT C5RAMMODE::#OFF C6LUT::#OFF C6RAMMODE::#OFF
            CCY0::#OFF CDI1MUX::#OFF CEUSED::#OFF CFF::#OFF CFFMUX::#OFF CFFSRINIT::#OFF
            CLKINV::CLK COUTMUX::C5Q COUTUSED::#OFF CUSED::#OFF D5FFSRINIT::SRINIT0
            D5LUT:Mmux_in[3]_GND_1_o_mux_13_OUT11:#LUT:O5=((~A5*((~A2*(A3*A4))+(A2*(~A3*~A4))))+(A5*((~A2*~A3)+(A2*(A3+A4)))))
            _BEL_PROP::D5LUT:BEL:D5LUT D5RAMMODE::#OFF D6LUT::#OFF D6RAMMODE::#OFF
            DCY0::#OFF DFF::#OFF DFFMUX::#OFF DFFSRINIT::#OFF DOUTMUX::D5Q DUSED::#OFF
            PRECYINIT::#OFF SRUSED::0 SYNC_ATTR::ASYNC WA7USED::#OFF WA8USED::#OFF
            WEMUX::#OFF A5FF:out_3: B5FF:out_2: C5FF:out_1: D5FF:out_0: "

The second section about interconnections settings shows the switch matrix configuration in plain-text. The connections between the static wires in the interconnection fabric are called PIP in Xilinx terminology, which stands for Programmable Interconnect Point [1].

net "in_1_IBUF" ,
  outpin "in<1>" I ,
  inpin "out_0" A4 ,
  inpin "out_0" B3 ,
  inpin "out_0" C3 ,
  inpin "out_0" D3 ,
  pip BIOB_X12Y0 BIOB_IBUF2_PINW -> BIOB_IBUF2 ,
  pip BIOI_OUTER_X12Y0 BIOI_OUTER_IBUF1 -> D_ILOGIC_IDATAIN_IODELAY_S ,
  pip BIOI_OUTER_X12Y0 D_ILOGIC_IDATAIN_IODELAY_S -> D_ILOGIC_SITE_S ,
  pip BIOI_OUTER_X12Y0 D_ILOGIC_SITE_S -> FABRICOUT_ILOGIC_SITE_S ,  #  _ROUTETHROUGH:D:FABRICOUT "XDL_DUMMY_BIOI_OUTER_X12Y0_ILOGIC_X9Y0" D -> FABRICOUT
  pip BIOI_OUTER_X12Y0 FABRICOUT_ILOGIC_SITE_S -> IOI_INTER_LOGICOUT7 ,
  pip BIOI_OUTER_X12Y0 IOI_INTER_LOGICOUT7 -> IOI_LOGICOUT7 ,
  pip CLEXM_X14Y2 CLEXM_LOGICIN_B32 -> M_A4 ,
  pip CLEXM_X14Y2 CLEXM_LOGICIN_B39 -> M_B3 ,
  pip CLEXM_X14Y2 CLEXM_LOGICIN_B47 -> M_C3 ,
  pip CLEXM_X14Y2 CLEXM_LOGICIN_B56 -> M_D3 ,
  pip INT_X14Y2 NL1E3 -> LOGICIN_B32 ,
  pip INT_X14Y2 NL1E3 -> LOGICIN_B39 ,
  pip INT_X14Y2 NR1E0 -> LOGICIN_B47 ,
  pip INT_X14Y2 NR1E0 -> LOGICIN_B56 ,
  pip IOI_INT_X12Y0 LOGICOUT7 -> EE2B0 ,
  pip IOI_INT_X14Y0 EE2E0 -> NR1B0 ,
  pip IOI_INT_X14Y1 NR1E0 -> NL1B3 ,
  pip IOI_INT_X14Y1 NR1E0 -> NR1B0 ,

The PIP syntax is explained in the comment of the same file:

# pip <tile> <wire0> <dir> <wire1> , # [<rt>]

The wire syntax is the following (from FpgaTools):

1-wire: {NL, NR, EL, ER, SL, SR, WL, WR} 1 {B, E} {0, 1, 2, 3}
2-wire: {NN, NE, EE, SE, SS, SW, WW, NW} 2 {B, E} {0, 1, 2, 3}
4-wire: {NN, NE, EE, SE, SS, SW, WW, NW} 4 {B, E} {0, 1, 2, 3}

B: begin
E: end

NL: North-Left          NN: North-North
NR: North-Right         NE: North-East
EL: East- Left          EE: East-East
ER: East-Right          SE: South-East
SL: South-Left          SS: South-South
SR: South-Right         SW: South-West
WL: West-Left           WW: West-West
WR: West-Right          NW: North-West

For example:

pip INT_X14Y2 NL1E3 -> LOGICIN_B32 ,

At the interconnection matrix INT_X14Y2, the 1-block-long wire coming from North-Left is connected to the logic input B32 (LOGICIN_B32).

[1](1, 2) From the bitstream to the netlist http://www.univ-st-etienne.fr/salware/Bibliography_Salware/FPGA%20Bistream%20Security/Article/Note2008.pdf
[2]Debit project repository http://code.google.com/p/debit/
[3]How to read an NCD file http://www.fpgadeveloper.com/2011/06/how-to-read-an-ncd-file.html