IceStorm project

In the same comment thread is also discussed about the IceStorm project [1], which aimed at reverse-engineering the bitstream format of the Lattice iCE40.

I even bought a stick to give a try! [2]

They managed to have the complete software chain open source: from verilog to bitstream. The stick features the iCE40HX-1k FPGA chip from Lattice (datasheet: [DS1040], digikey: [3] approx. 5€).

Is it interesting for dynamique partial reconfiguration?

According to [DS1040] (v3.1, p.3-17), in slave SPI mode, the maximum input clock is 25MHz (readback is 15MHz). The FPGA can be configured using SPI interface in ~25ms (with medium frequency SPI mode, 24MHz). The bitstream is 34112KB ([TN1248], p.11). Lattice does not seem to have developped any user-friendly way to use partial reconfiguration.

According to [TN1248], p.4, the SPI configuration flow requires a CRESET_B to restart the configuration sequence.

[TN1248], p.18:

After driving CRESET_B High or allowing it to float High, the AP must wait a minimum of 300 μs, allowing the iCE40 FPGA to clear its internal configuration memory.

Looking at [HB1011] and [DS1040], there does not seem to be any JTAG interface in this chip family.

Conclusion

Partial reconfiguration seems impossible with the iCE40 FPGA.

References