Matching the Xilinx bitstream with the Spartan-6 silicium die

Note: Actually what I had drawn in yesterday's diagrams was wrong, and I updated last post today (logical tiles coordinates start from top left corner, while (row, major, minor) start from bottom left). I found the issue when trying to match the bitstream with the expected die configuration. Since everything is reversed, I switch my simple_and configuration to the other side of the die at the pins P57, P58 and P59.

Spartan6 internal configuration

In [UG380] (v2.5, at p. 91) is described the different kinds of configuration memory frames:

The internal Xilinx configuration has three blocks:

  1. block 0: switch matrix and LUT configuration (routing and logic blocks)
  2. block 1: BRAM configuration (RAM blocks)
  3. block 2: IOB configuration (I/O blocks)
Block type Start word End word Length (words) Num frames Frame length (words)
Block 0 0 131,299 131,300 (4 * 505) = 2020 65
Block 1 131,300 168,739 37,440 (4 * 144) = 576 65
Block 2 168,740 169,635 896 1 896

This table does not really matches the data given in [UG380]:

It seems that 2 padding frames are added to each row in the block 0, and that 1 word in added to the block 2.

Frame addressing

According to [UG380] (at p. 95, v2.5):

To get more information about the way each frame is addressed in the bitstream, I tried to use the bitgen command option: -g DebugBitstream:Yes as decribed in [UG628] (v14.7, p. 232). Unfortunately, bitgen fails with the error:

ERROR:Bitstream - DebugBitstream is not supported. An AutoIncrement bit file will be created.

I asked about it [1] on the Xilinx User Community Forums. According to a feature request on the Torc project [2], this option (DebugBitstream) is not supported on Spartan-6.


[UG380](1, 2, 3) Xilinx, Spartan-6 FPGA Configuration,
[UG628]Xilinx, Command Line Tools User Guide,
[1]Xilinx, DebugBitstream is not supported,
[2]Torc project, Feature request #11 Spartan6 bitstream support,