Note: Actually what I had drawn in yesterday's diagrams was wrong, and I updated last post today (logical tiles coordinates start from top left corner, while (row, major, minor) start from bottom left). I found the issue when trying to match the bitstream with the expected die configuration. Since everything is reversed, I switch my simple_and configuration to the other side of the die at the pins P57, P58 and P59.
Spartan6 internal configuration
In [UG380] (v2.5, at p. 91) is described the different kinds of configuration memory frames:
The internal Xilinx configuration has three blocks:
- block 0: switch matrix and LUT configuration (routing and logic blocks)
- block 1: BRAM configuration (RAM blocks)
- block 2: IOB configuration (I/O blocks)
|Block type||Start word||End word||Length (words)||Num frames||Frame length (words)|
|Block 0||0||131,299||131,300||(4 * 505) = 2020||65|
|Block 1||131,300||168,739||37,440||(4 * 144) = 576||65|
This table does not really matches the data given in [UG380]:
It seems that 2 padding frames are added to each row in the block 0, and that 1 word in added to the block 2.
According to [UG380] (at p. 95, v2.5):
To get more information about the way each frame is addressed in the bitstream, I tried to use the bitgen command option: -g DebugBitstream:Yes as decribed in [UG628] (v14.7, p. 232). Unfortunately, bitgen fails with the error:
ERROR:Bitstream - DebugBitstream is not supported. An AutoIncrement bit file will be created.
|[UG380]||(1, 2, 3) Xilinx, Spartan-6 FPGA Configuration, http://www.xilinx.com/support/documentation/user_guides/ug380.pdf|
|[UG628]||Xilinx, Command Line Tools User Guide, http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/devref.pdf|
|||Xilinx, DebugBitstream is not supported, http://forums.xilinx.com/t5/Installation-and-Licensing/DebugBitstream-is-not-supported/m-p/511251|
|||Torc project, Feature request #11 Spartan6 bitstream support, http://sourceforge.net/p/torc-isi/feature-requests/11/|