After testing and debuging a lot my microcontroller code of partial reconfiguration, I noticed that it does not even work with the official tool!
According to this post of the Xilinx forum : some other people already tried the same, and seemed to fail. I get the same behavior.
In addition, another issue is described in Advanced Partial Run-time Reconfiguration on Spartan-6 FPGAs 
While we have not been able to configure Spartan-6 devices using the JTAG configuration port, full read and writes access to the fabric was possible using the internal configuration access port (ICAP) in Slave SelectMAP mode.
Still I progressed a lot on my bitstream disassembly tool and generation on microcontroller. I generate now dynamically the initial and ending commands as documented in the Xilinx manuals.
Update: The Spartan-6 is not in the supported FPGAs for the ISE Design suite for partial reconfiguration. See .
Note "from the future": Please see the next posts in this blog to discover that it is actually possible to reconfigure on-the-fly using the JTAG interface.
|||Xilinx forums, http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Spartan-6-difference-based-partial-reconfiguration-problem/td-p/139756|
|||Dirk Koch, Advanced Partial Run-time Reconfiguration on Spartan-6 FPGAs, https://www.duo.uio.no/bitstream/handle/10852/8851/fpt10koch_demo.pdf|
|||Xilinx, Partial Reconfiguration in the ISE Design Suite, http://www.xilinx.com/tools/partial-reconfiguration.htm|