The Xilinx application note [XAPP290] for Difference-Based Partial Reconfiguration. The document explains how to update the configuration of a Virtex FPGA without stopping it. Actually it does also apply to Spartan-6.

The usage is very easy:

1. Create an initial bitstream file .bit.
2. Change the initial configuration using FPGA editor or another tool and save the resulting .ncd file under a new name.
3. Call bitgen from command line with the -g ActiveReconfig (to keep the FPGA running during reconfiguration) and with -r to generate a new bitstream containing only the differences from the previous one.

Example run with simple_and and simple_xor (simple_xor_diff being an update from simple_and):

$ bitgen -g ActiveReconfig:Yes -r simple_and.bit simple_xor.ncd simple_xor_diff.bit
Release 14.7 - Bitgen P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
Loading device for application Rf_Device from file '6slx9.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/.
   "simple_and" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3

Wed Apr 23 09:38:23 2014

Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Loading bitfile simple_and.bit...
Saving bit stream in "simple_xor_diff.bit".
Making partial bitfile...
There were 2 frames different between simple_and.bit and
simple_xor.ncd;UserID=0xFFFFFFFF.
Bitstream generation is complete.

We can see that the resulting bitstream is much shorter, and basically contains two configuration frames only. The FAR_MAJ command gives the address of the start of the bits.

const uint8_t bitstream[508] = {
[...]
0x30, 0x22, /* 3022 packet hdr: type=1 op=WRITE (0x2) reg=FAR_MAJ (0x1) len=2 */
0x00, 0x0d, /* 000d */
0x00, 0x15, /* 0015 */
0x30, 0xa1, /* 30a1 packet hdr: type=1 op=WRITE (0x2) reg=CMD (0x5) len=1 */
0x00, 0x01, /* 0001 command: WCFG (01) */
0x50, 0x60, /* 5060 packet hdr: type=2 op=WRITE (0x2) reg=FDRI (0x3) len=0 */
0x00, 0x00, /* 0000 word count part1: 00000000 */
0x00, 0xc3, /* 00c3 word count part2: 000000c3 (195 +2) */
0x00, 0x00, /* 0000 row 0, frame 0 (maj 0, min 0) */
[...bits...]
}

FAR_MAJ: 0x000d = 0x0000_0000_0000_1101 -> (blk:0, row:0, maj:13)
FAR_MIN: 0x0015 = 0x0000_0000_0001_0101 -> (block RAM:0, min:21)

I used the following files for my tests:

• Simple AND gate: simple_and.bit
• Simple OR gate: simple_or.bit
• Simple OR gate, as a difference bitstream from the simple AND gate: simple_or_diff.bit
• Extraction of the bitstream informations of the difference file above: simple_or_diff.c