Readback the Spartan-6 configuration registers over JTAG

Since long time, I failed reading back data from the Spartan-6 configuration registers (STAT, COR1, COR2), even though the sequence is described in the Configuration Register Read Procedure (JTAG) section [UG380] (p.117, v2.5).

This part contains several incoherencies which led me not to follow each step blindly. Actually, I discovered today, that it is very important not to go back to RTI state in the JTAG TAP state machine during the sequence (Table 6-5), otherwise the data output is always zero.

Ready
IDCODE(JTAG): 0x24001093
IDCODE(BITS): 0x24001093
CTL    (BITS): 0x0081
STAT   (BITS): 0x373C
COR1   (BITS): 0x3D08
COR2   (BITS): 0x09EE
BOOTSTS(BITS): 0x0001

Various status and configuration registers can now be read... and the internal FPGA configuration as well!

Extracts of the Xilinx documentation for later references

[UG380]Spartan-6 FPGA Configuration http://www.xilinx.com/support/documentation/user_guides/ug380.pdf