The JTAG port of the Spartan-6 FPGA was hand-soldered to the wire and connected to the STM32 microcontroller.
The JTAG TAP state machine
Now can we enter the FPGA using the microcontroller? [UG380] explains how to do so.
JTAG ports have a funny bitstream-controlled state machine for filling variable-length instruction- and data-registers (picture taken from Xilinx documentation). It is like walking in a maze with no light: you have to count your steps (clock ticks) and go to left or right (0 or 1) at the right step having no feedback.
On the top the TDO output pin, on the bottom the TCK clock pin.
1100 1001 0000 1000 0000 0000 0000 0010 0100 (least significant bit is first) -> 0x240001093 -> Xilinx XC6LX9
Hello dear Spartan-6 LX9! I've found you!
As reference, [UG380] gives the ID code for each silicon
ps: Actually there is a trick for the binary maze: you go five time in a row to the branch marked '1' and you always go back to "Test-Logic-Reset". It works in any state of the state machine. Check the state machine...
|[UG380]||(1, 2) Xilinx, Spartan-6 FPGA Configuration user guide http://www.xilinx.com/support/documentation/user_guides/ug380.pdf|