After having found the location of the LUT in the FPGA die, their equations can be reconfigured.
FLR_SID_READ_TARGET [TX8]0x0002000000000000 [RX8]0x0082005555555555 FLR_SID_SET_LUT_EQU [TX8]0x0121030f02050000 [TX8]0xffffffffffffcccc [RX8]0x00a1005555555555 FLR_SID_SET_LUT_EQU [TX8]0x0121030f02060000 [TX8]0xfffffffffffffffe [RX8]0x00a1005555555555 FLR_SID_WRITE_TARGET [TX8]0x0003000100020000 [RX8]0x0083005555555555 FLR_SID_WRITE_TARGET [TX8]0x0003000400020000 [RX8]0x0083005555555555
Note: this example is based on a preliminary implementation. The read target request actually uses hard-coded bitstream data, since readback was not yet implemented.
Advantages of the live reconfiguration over a full FPGA-based solution
The initial FPGA-only solution requires external input for the trigger pattern. To save pins, the match[7:0] bus could be replaced by a shift register. Still, this solution does not allow to mask the value of some bits in the data flow, and a second shift register would be required for the mask... inserting new LUT layers, and delays.
The live reconfigurable solution offers more flexibility at the cost of a high reconfiguration delay.
|[FLR]||FPGA Live Reconfiguration protocol specitications https://vjordan.info/flr/|