Spartan-6 maximum JTAG clock is 18-33MHz according to "Table 3: Maximum JTAG Clock Frequencies" in [DS593] (v1.4, p. 8).
The Spartan-6 at speed grade -1L is limited to 18MHz, while other speed grades (-2, -3N, and -3) allows a TCK of 33MHz. See "Configuration Switching Characteristics" in [DS162] (v3.1.1, p. 54). Regarding the SelectMAP interface of the Spartan-6 LX9, the maximum configuration clock (CCLK) is 50MHz for speed grades -2 and above.
SelectMAP implementation
The implementation follows the documentation about "Microprocessor-Driven SelectMAP Configuration" from [UG380] (v2.7, p. 34) (further described in the old [XAPP502] and the newer [XAPP583]).
One important thing is to enable CCLK as configuration clock.
I am tryig to use the SelectMAP interface from the microconroller, but it is not working so far. I will update this post.
About bit swapping:
| 0xAA99 | (config. word) | 0xAA | 0x99 | (config. bytes) | A A | 9 9 | (hex nibbles) | 1010 1010 | 1001 1001 | (original bits) | 0101 0101 | 1001 1001 | (swapped bits) | D15 <-> D8 | D7 <-> D0 | (SelectMAP pins)
Update 2015.05.13
Apparantly, you have should use the .bin file for SelectMAP configuration (not the .bit file). I generated both and they have not the same content (as I previously expected).
The 16-bit parallel configuration (16x SelectMAP) from microcontroller now works, but I had to make an unexpected change on the clock CCLK termination resistors (2x 100Ω): remove the resistor to Vcc, while keeping the one to ground, so to lower the voltage of the clock. This goes against the recommendation of the Xilinx documentation [UG380].
What if ...?
I get status gives all bit at 0. Maybe PROGRAM_B is held low?
I send the configuration as serial data on D0 with mode settings for slave SelectMAP (M[1:0] = 10)? Actually, I works too. The slave serial setting (*``M[1:0] = 11``) is redundant.*
Persistant SelectMAP pins and readback settings
draft
- ::
- INFO:Bitgen:278 - Setting the Persist option to "Yes" with the CONFIG_MODE
- constraint value "UnSpecified" will result in the 8-bit SelectMap port being persisted.
[UG625] (v14.5, p.70) "Configuration Mode". Strangely, according to this document, the Spartan-6 is not in the supported target devices. The option works anyway:
# SelectMAP slave, 16-bit mode with "Persist" option. CONFIG CONFIG_MODE=S_SELECTMAP16+READBACK;
References
| [DS593] | Xilinx, Platform Cable USB II documentation, http://www.xilinx.com/support/documentation/data_sheets/ds593.pdf |
| [DS162] | Xilinx, Spartan-6 FPGA Data Sheet: DC and Switching Characteristics, http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf |
| [1] | Xilinx, ISE Design Suite 14.7 manual, http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/pp_db_readback_options.htm |
| [UG625] | Xilinx, Constraints Guide, http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf |
| [UG380] | (1, 2) Xilinx, http://www.xilinx.com/support/documentation/user_guides/ug380.pdf |
| [XAPP502] | Xilinx, Application note, http://www.xilinx.com/support/documentation/application_notes/xapp502.pdf |
| [XAPP583] | Xilinx, Application note (Specific to 7-series), http://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf |
| [2] | Love this answer: http://stackoverflow.com/a/1155589 |