We saw in the previous post, that "NL1E3 -> LOGICIN_B32" was used by the slice M design. Those PIP names match the names used in the list here  for interconnection switches in FLR protocol: NL1E3 -> LOGICIN_B32 is the switch id 2168.
The switch is in the following wire chain:
in -> [...] -> NL1E3 -> LOGICIN_B32 -> M_A4 -> [...] -> out
Question: Is it possible to reconfigure an individual switch in the Spartan-6 switch matrix using the partial reconfiguration feature without stopping the FPGA?
FLR get switch request
In , it was found that the switch matrix configuration bitstream is the same for all switch matrixes of the Spartan-6 FPGA. In other words, the bits controlling the activation of a switch in the matrix are always located at the same bitstream position, no matter if the switch is not actually available in the silicium die.
Knowing the switch id, the same operation can be applied to any switch matrixes.
FLR_SID_READ_TARGET [TX8]0x0002000f00001500 <- read the 20 first minors at (row:0, maj:15) [RX8]0x0082005555555555 FLR_SID_GET_SWITCH [TX8]0x0030000f0d087800 <- get the status of the switch 2168 in matrix:13 [RX8]0x00b0000000000001 <- the switch is activated! (bit the 1 at the end) FLR_SID_GET_SWITCH [TX8]0x0030000f0d087900 <- get the status of the switch 2169 [RX8]0x00b0000000000000 <- the switch is not activated (ok)
Note: this preliminary implementation does not follow the FLR specifications.
FLR set switch request
[...] FLR_SID_SET_SWITCH [TX8]0x0031000f0d087800 <- disable the switch 2168 in matrix:13 [RX8]0x00b1000000000000 FLR_SID_WRITE_TARGET [TX8]0x0003000000157800 <- write the patched switch matrix to target [RX8]0x0083005555555555
By activating/desactivating the switch id 2168, one can disable or enable the 4th input in the LUT_A (driving the 4th output). See previous post for details about the implemented design.
Experimental results comfirm this dynamic behavior.
|||List of the Programmable Interconnect Point (PIP) in the Xilinx Spartan-6 LX9 http://vjordan.info/flr/switches_xc6lx9.html|
|||From the bitstream to the netlist http://www.univ-st-etienne.fr/salware/Bibliography_Salware/FPGA%20Bistream%20Security/Article/Note2008.pdf|