The internal configuration of most of the FPGA currently available (such as the Xilinx Spartan-6) are SRAM-based. Since those configuration bits are directly used by the internal blocks of the FPGA, their behavior is changed right after changing the corresponding bits in the SRAM configuration.

In my previous posts, I analyzed the Spartan-6 architecture, and checked whether the internal FPGA configuration could be changed through dynamic partial reconfiguration, in other words, while the FPGA is active. Here is a summary of the results.

Dynamic reconfiguration possibilities:

Ⓐ Switch matrix

It is possible to enable or disable on single switch dynamically.

→ See SET_SWITCH request.

Ⓑ Logic in/out

not tested yet

→ See SET_SWITCH request.

Ⓒ LUT equation

It is possible the change each LUT equation (A, B, C, or D) dynamically.

→ See SET_LUT_EQU request.

Ⓓ D flip-flop and multiplexer

It is possible the change the multiplexer setting dynamically. The initial value of the DFF (on reset) can be changed as well, but it has not been tested yet.

→ See SET_LOGIC_CONF request.