The project FpgaTools [1] contains a tool to interpret the Xilinx bitstreams into plaintext floorplans: bit2fp.
Let's see what happens on my simple example:
$ ./bit2fp simple_and.bit fpga_floorplan_format 1 dev y0 x21 IOB 1 ostd LVCMOS33 dev y0 x21 IOB 1 strength 12 dev y0 x21 IOB 1 slew SLOW dev y0 x21 IOB 1 O_used dev y0 x21 IOB 1 suspend 3STATE dev y0 x21 IOB 2 istd LVCMOS25 dev y0 x21 IOB 2 bypass_mux I dev y0 x21 IOB 2 imux I dev y0 x21 IOB 3 istd LVCMOS25 dev y0 x21 IOB 3 bypass_mux I dev y0 x21 IOB 3 imux I dev y4 x22 LOGIC 0 D6_lut_str A3*A5 dev y4 x22 LOGIC 0 D_outmux O6 net 1 sw y2 x21 NN2E1 -> LOGICIN_B15 net 2 sw y3 x21 LOGICOUT0 -> SR1B1 net 3 sw y3 x21 LOGICOUT7 -> SL1B0 net 4 sw y4 x21 LOGICOUT22 -> NN2B1 net 5 sw y4 x21 SR1E1 -> LOGICIN_B58 net 6 sw y4 x21 SL1E0 -> LOGICIN_B56 net 7 sw y2 x22 D1_OLOGIC_SITE_S -> OQ_OLOGIC_SITE_S net 8 sw y2 x22 OQ_OLOGIC_SITE_S -> TIOI_OUTER_O1 net 9 sw y3 x22 D_ILOGIC_IDATAIN_IODELAY -> D_ILOGIC_SITE net 10 sw y3 x22 D_ILOGIC_IDATAIN_IODELAY_S -> D_ILOGIC_SITE_S net 11 sw y3 x22 D_ILOGIC_SITE -> FABRICOUT_ILOGIC_SITE net 12 sw y3 x22 D_ILOGIC_SITE_S -> FABRICOUT_ILOGIC_SITE_S
A graphical representation of the connexions with the help of Xilinx FPGA Editor. Note: the coordinates XnYm are not the same as the ones used in FPGA Editor.

From input to output:
The bloc Y0X21 configures the input pads (i/o stantard, drive strength, slew type, ...):
IOB 2 istd LVCMOS25 IOB 2 bypass_mux I IOB 2 imux I IOB 3 istd LVCMOS25 IOB 3 bypass_mux I IOB 3 imux I
The bloc Y3X22 is ???:
D_ILOGIC_IDATAIN_IODELAY -> D_ILOGIC_SITE -> FABRICOUT_ILOGIC_SITE D_ILOGIC_IDATAIN_IODELAY_S -> D_ILOGIC_SITE_S -> FABRICOUT_ILOGIC_SITE_S
The bloc Y3X21 is the switch matrix of Y3X22 to connect to the interconnexion fabric:
LOGICOUT0 -> SR1B1 LOGICOUT7 -> SL1B0
The bloc Y4X21 is the switch matrix of Y4X22 to connect to the interconnexion fabric:
SR1E1 -> LOGICIN_B58 SL1E0 -> LOGICIN_B56
The bloc Y4X22 is the "Configurable Logic Block" (CLB), which contains a SLICEX and a SLICEL, each featuring 4 LUTs (6 inputs, 2 outputs):
LOGIC 0 D6_lut_str A3*A5 LOGIC 0 D_outmux O6
The bloc Y4X21 is the switch matrix of Y4X22 to connect to the interconnexion fabric:
LOGICOUT22 -> NN2B1
The bloc Y2X21 is the switch matrix of Y2X22 to connect to the interconnexion fabric:
NN2E1 -> LOGICIN_B15
The bloc Y2X22 is ???:
D1_OLOGIC_SITE_S -> OQ_OLOGIC_SITE_S OQ_OLOGIC_SITE_S -> TIOI_OUTER_O1
The bloc Y0X21 configures the output pad (i/o stantard, drive strength, slew type, ...):
dev y0 x21 IOB 1 ostd LVCMOS33 dev y0 x21 IOB 1 strength 12 dev y0 x21 IOB 1 slew SLOW dev y0 x21 IOB 1 O_used dev y0 x21 IOB 1 suspend 3STATE
[1] | FpgaTools https://github.com/Wolfgang-Spraul/fpgatools |