Spartan-6 SelectMap port length matching

Update 2015.03.09 it is quite funny that CERN made a video exactly on the same day (2015.03.03) about KiCAD new features for trace length matching. Thanks CERN! See [1].

Further experiences with KiCAD, FreeRouting and track length matching.

FreeRouting has a quite nice support for fixed length tracks. It displays useful information about the remaining minimum and maximum length of the track. There is still a very annoying issue that I couldn't manage to solve: how to create "slaloms"/"zigzags" with the track when the destination pad is too close? Because of the automatic tighting system it was pretty much impossible to keep a track at a fixed location, and I was unable to really use FreeRouting from end-to-end.

My strategy:

  • use FreeRouting to find out what is the maximum length among the tracks and a good layout draft.
  • use KiCAD to finish the layout, by checking the length of each track and drawing longer tracks when needed.

Example

The SelectMAP port is a 16-bit parallel bus which can go up to 50MHz according the datasheet ([DS162] v3.1.1, p.54). The propagation time in a PCB track depends to the layer (faster propagation in outer layer), see [2].

Cycle time      : 50MHz -> period is 20ns = 20000ps
Propagation time: approx. 10ps/mm in PCB tracks

For this signal, length matching of the tracks is not required since the margin is huge (even a difference of 10cm in length would only make a delay of 1ns).

The clock and data lines of SelectMap bus are connected to the connector with a length between 15 and 17mm.

References

[1]Kicad - Differential pair routing and trace length matching, https://www.youtube.com/watch?v=chejn7dqpfQ
[DS162]Spartan-6 FPGA Data Sheet: DC and Switching Characteristics, http://www.xilinx.com/support/documentation/data_sheets/ds162.pdf
[2]Peter Alfke, Printed Circuit Board Design Considerations, http://web.ewu.edu/groups/technology/Claudio/ee260/LabDocuments/pcb_xilinx.pdf