Spartan6 Slice M dynamic reconfiguration

In my previous post, I documented the configuration options available in the bitstream for the Slice M logic blocks. In order to check whether they are dynamically reconfigurable or not, I experimented with the OUTMUX multiplexer.

When D5Q ① is selected by OUTMUX, the output DMUX is registered, when O5 ② is selected, the output DMUX is not more registered.

According to my experimental results, this settings can be changed dynamically, hence switching between registered and unregistered output while the FPGA is active.

Experimental requests

FLR_SID_READ_TARGET
[TX8]0x0002000f14000700 <- Readback the FPGA config at (row:0, maj:15, min:20)
[RX8]0x0082005555555555    with length:7 (from min:20 to min:26)
FLR_SID_GET_LOGIC_CONF
[TX8]0x0022000f0d010700 <- Get the current CLB config
[RX8]0x02a2005555555555
[RX8]0x0000000000000000
[RX8]0x0000000000000000 <- OUTMUX is set to 0 (D5Q input) for all LUT
FLR_SID_SET_LOGIC_CONF
[TX8]0x0223000f0d010700 <- Set a new CLB configuration
[TX8]0x0000000000000000
[TX8]0x0000000055554444 <- Set OUTMUX to 4 (O5 input) for all LUT
[RX8]0x00a3005555555555
FLR_SID_WRITE_TARGET
[TX8]0x0003000000070700 <- Write the modified FPGA config in the working
[RX8]0x0083005555555555    buffer to the target (offset:0, length: 7)
FLR_SID_READ_TARGET
[TX8]0x0002000f14000700 <- Read the FPGA config at the same location
[RX8]0x0082005555555555    to check if the config was changed
FLR_SID_GET_LOGIC_CONF
[TX8]0x0022000f0d010700
[RX8]0x02a2005555555555
[RX8]0x0000000000000000
[RX8]0x0000000000004444 <- OUTMUX is was set to 4 (O5), now confirmed

Experimental check on breadboard showed that the output was correctly unregistered after running those requests.

[1]FPGA Live reconfiguration protocol http://vjordan.info/flr/