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  1. Spartan6 LX9 to STM32 F4 loop

    The experimental solution with STM32F4 and XC6LX9 discrete development boards.

    This problem is that many pins are hard-wired to some specific features. For example, the SelectMap port cannot be used on my current FPGA board. The goal would be to have 32-bit input and output between the FPGA and the …

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  2. Proposal for a dynamic and compact state machine on Spantan-6

    My proposal for an ultra compact 4-bit FSM fitting in one Spartan-6 CLB only, by using dynamic reconfiguration. The overall state machine being itself dynamically reconfigured, allowing to create or remove states, or change transitions or state output...

    Important limitation: so as to make it fit in one CLB only …

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  3. Spartan-6 dynamic reconfiguration summary

    The internal configuration of most of the FPGA currently available (such as the Xilinx Spartan-6) are SRAM-based. Since those configuration bits are directly used by the internal blocks of the FPGA, their behavior is changed right after changing the corresponding bits in the SRAM configuration.

    In my previous posts, I …

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  4. How to read an .ncd file

    The Xilinx design work flow, as described in [1]:

    By the way, it seems that the Debit project is no more available at the address given in the document, but the source code repository can still be found at [2].

    The .ncd file is the most important file, which contains …

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  5. Spartan6 Slice M dynamic reconfiguration

    In my previous post, I documented the configuration options available in the bitstream for the Slice M logic blocks. In order to check whether they are dynamically reconfigurable or not, I experimented with the OUTMUX multiplexer.

    When D5Q ① is selected by OUTMUX, the output DMUX is registered, when O5 …

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  6. Spartan6 Slice M configuration

    The generic building block to make a FPGA is the logic block, which is composed of look-up table and flip-flop. Each FPGA maker has its own design and terms for those Logic Element:

    • Xilinx Spartan 6: Slice M, L, or X with 4 LUT (6 inputs) and 8 Flip-flops, packed …
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  7. Xilinx ISE: preventing registers in IOB

    When creating a design with a registered output, the D Flip-Flop of the final output (just before the FPGA pads) are moved to IOB blocks. See [1]

    Note: Do not try to move the D Flip-Flop to another location in PlanAhead, the tool will behave fine, but will not save …

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  8. High speed serial bus generation using Spartan-6

    My goal is to generate an 8-bit serial data signal and its clock (similar to SPI bus). High-speed serialization can be achieved using SerDes (Serializer Deserializer) dedicated logic in Xilinx Spartan-6 FPGA.

    This post is entirely based on the Xilinx application note [XAPP1064]. General clock configurations are also described in …

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  9. High speed serial trigger using Spartan-6 (improved)

    Implementation of a 8-bit shift register with automatic clear

    module shift_reg(
            clk,
            clear,
            shift_in,
            d_out
            );
    
    input                   clk;
    input                   clear;
    input                   shift_in;
    output [7:0]    d_out;
    reg    [7:0]    d_out;
    reg    [7:0]    count;  // "One Hot" encoding of the current register load
    reg                             reset;  // if 1, register is cleared at next …
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  10. High speed serial trigger using Spartan-6

    The serial trigger includes a shift register and a comparator. When the content of the register matches the expected pattern, the trigger output is set to high.

    First, how to create a simple 8-bit shift register in verilog?

    Implementation of a simple 8-bit shift register

    module shift_reg(
            clk,            // clock
            clear …
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  11. Readback the Spartan-6 configuration registers over JTAG

    Since long time, I failed reading back data from the Spartan-6 configuration registers (STAT, COR1, COR2), even though the sequence is described in the Configuration Register Read Procedure (JTAG) section [UG380] (p.117, v2.5).

    This part contains several incoherencies which led me not to follow each step blindly. Actually …

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  12. Reconfiguration of the trigger pattern

    After having found the location of the LUT in the FPGA die, their equations can be reconfigured.

    Example requests

    [FLR] requests:

    FLR_SID_READ_TARGET
    [TX8]0x0002000000000000
    [RX8]0x0082005555555555
    FLR_SID_SET_LUT_EQU
    [TX8]0x0121030f02050000
    [TX8]0xffffffffffffcccc
    [RX8]0x00a1005555555555
    FLR_SID_SET_LUT_EQU
    [TX8]0x0121030f02060000
    [TX8]0xfffffffffffffffe
    [RX8]0x00a1005555555555
    FLR_SID_WRITE_TARGET
    [TX8]0x0003000100020000
    [RX8]0x0083005555555555
    FLR_SID_WRITE_TARGET
    [TX8]0x0003000400020000
    [RX8]0x0083005555555555 …
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  13. Where is my LUT (in the Spartan-6 LX9)?

    You created your Verilog or VHDL design, and you want to create a placement constraint of some blocks that you plan to reconfigure later during runtime? The live reconfiguration server will need the bitstream coordinates to find those corresponding blocks in the internal FPGA configuration. Unfortunately, the (X, Y) from …

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  14. 8-bit data trigger with FPGA

    I want to create a super fast data trigger on 8-bit words. When the data bus matches the bit pattern, the trigger output is set to high.

    module pattern_match(
            input [7:0] data,
            input [7:0] match,
            output trigger
            );
    
    assign trigger = data == match;
    
    endmodule
    

    The corresponding schematic:

    And here is …

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  15. The FPGA model of fpgatools and sw_bitpos

    The FPGA model as defined in FpgaTools [1] with additional comments:

    struct fpga_model
    {
            /* return code */
            int rc; // if rc != 0, all function calls will immediately return
    
            const struct xc_die *die;
            /* array of the all the pins of the package */
            const struct xc6_pkg_info *pkg;
    
            int x_width, y_height;
            int center_x;
            int center_y …
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  16. SelectMAP configuration

    Unlike JTAG, the SelectMAP configuration interface seems to be equivalent to the ICAP (Internal Configuration Access Port), which has already been succeesfully used for partial reconfiguration with Spartan-6 (as opposed to the JTAG interface).

    The pinout of the Spartan-6 LX9 TQG144 is in [UG385] in table 2-2, p.28 (v2 …

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  17. Partial reconfiguration with XAPP290

    The Xilinx application note [XAPP290] for Difference-Based Partial Reconfiguration. The document explains how to update the configuration of a Virtex FPGA without stopping it. Actually it does also apply to Spartan-6.

    The usage is very easy:

    1. Create an initial bitstream file .bit.
    2. Change the initial configuration using FPGA editor or …
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  18. Matching the Xilinx bitstream with the Spartan-6 silicium die

    Note: Actually what I had drawn in yesterday's diagrams was wrong, and I updated last post today (logical tiles coordinates start from top left corner, while (row, major, minor) start from bottom left). I found the issue when trying to match the bitstream with the expected die configuration. Since everything …

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  19. XC6SLX9 die layout and bitstream

    The silicium layout of FPGAs is (always?) made of a repetitive pattern, hence the configuration system features a kind of coordinate system, in order to select which tile is being configured.

    The Xilinx configuration guide [UG380] and the documentation of the logic blocks [UG384] give some insights about the internal …

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  20. Bitstream analysis code

    Today I analyzed the Xilinx documentation about the bitstream format in [UG380] p.92 (v2.5), and I updated the C code converting bitstream into a C array for generating C comments at each configuration word.

    See the full file here: simple_and.c (~4MB) [1]

    All instructions are documented by …

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  21. Spartan-6 routing internals

    The project FpgaTools [1] contains a tool to interpret the Xilinx bitstreams into plaintext floorplans: bit2fp.

    Let's see what happens on my simple example:

    $ ./bit2fp simple_and.bit
    fpga_floorplan_format 1
    dev y0 x21 IOB 1 ostd LVCMOS33
    dev y0 x21 IOB 1 strength 12
    dev y0 x21 IOB 1 slew SLOW …
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  22. Hello (FPGA) World over STM32!

    The following verilog code was implemented using Xilinx ISE toolsuite:

    `timescale 1ns / 1ps
    
    module simple_and(
    input a1,
    input a2,
    output a3
    );
    
    assign a3 = a1 & a2;
    
    endmodule
    

    At the end, the tool generate a bitstream: a binary file containing raw data ready to be uploaded to the FPGA over …

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  23. Reading the Xilinx IDCODE over JTAG

    The JTAG port of the Spartan-6 FPGA was hand-soldered to the wire and connected to the STM32 microcontroller.

    The JTAG TAP state machine

    Now can we enter the FPGA using the microcontroller? [UG380] explains how to do so.

    JTAG ports have a funny bitstream-controlled state machine for filling variable-length instruction- …

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  24. First step: prepare a nice welcoming desk

    A nice desk makes it easier to find everyday motivation. The STM32 microcontroller, the Xilinx Spartan-6, and their respective debuggers are waiting to work together (see on the left)! (^_^)

    Hardware information

    • the Xilinx Spartan-6 LX9 FPGA board.

    Really nice little board with 32-MByte SDRAM and 8-Mbyte SPI flash. The …

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