A CLB tile as described in Xilinx documentation [UG384], p.7 (v1.1):

• Ⓐ logic to interconnect
• Ⓑ horizontal interconnect to vertical
• Ⓒ horizontal to horizontal interconnect

One switch in the switch matrix on the old XC4000:

With a 6-bit memory bitfield, 6 switched can be controlled at one intersection. Hence, all connection possibilities can be achieved:

012345
------
000001| a-b
000010| b-d
000100| a-d
001000| a-c
010000| c-d
100000| b-d

Of course, only two bits can be enabled at a time, otherwise one wire would be connected to two other wires.

Unfortunately, I don't find anything matching this in the bit stream of the Spartan-6.

[UG384]

Spartan-6 FPGA Configurable Logic Block http://www.xilinx.com/support/documentation/user_guides/ug384.pdf