Where is my LUT (in the Spartan-6 LX9)?

You created your Verilog or VHDL design, and you want to create a placement constraint of some blocks that you plan to reconfigure later during runtime? The live reconfiguration server will need the bitstream coordinates to find those corresponding blocks in the internal FPGA configuration. Unfortunately, the (X, Y) from the constraint file (.ucf) do not match the (row, major, minor, idx) from the bitstream.

How to create a placement constraint?

Using PlanAhead in the Xilinx FPGA design toolkit, each LUT can be place manually.

A simple drag-and-drop will do the job. When saving the changes, PlanAhead will generate those plain-text constraints in the corresponding .udf file of the project.

# PlanAhead Generated physical constraints

INST "trigger<7>" BEL = C6LUT;
INST "trigger<7>" LOC = SLICE_X20Y61;
INST "trigger<7>_SW0" BEL = B6LUT;
INST "trigger<7>_SW0" LOC = SLICE_X20Y61;

How to find back the position in the bitstream?

In the device tab:

The Spartan-6 LX9 has 4 rows of 2 clock regions each. The row 0 is the bottom of the chip along the bank 0.

Each row is organized into columns of similar blocks (SLICE_L, SLICE_M, BRAM, etc) called majors

Concerning the SLICE_M, two arrays of LUTs are found: M type (with additional fonctionalities to implement memory) and X type (with no additional fonctionality).

Final position of the LUT3 equation:

  • row = 3 in [0~3]
  • maj = 15 in [0~17]
  • idx = 2 [in 0~15]
  • minor = 21 and 22 in [0~30] (LUT_B is second half)

Let us check the output of bit2c:

/* frame 1951 (row 3, maj 15, min 22) */
{
/* 126899 */    0x0000, /* dw 126815 empty */
/* 126900 */    0x0000, /* dw 126816 empty */
/* 126901 */    0x0000, /* dw 126817 empty */
/* 126902 */    0x0000, /* dw 126818 empty */
/* 126903 */    0x0000, /* dw 126819 empty */
/* 126904 */    0x0000, /* dw 126820 empty */
/* 126905 */    0x0000, /* dw 126821 empty */
/* 126906 */    0x0000, /* dw 126822 empty */
/* 126907 */    0x0300, /* dw 126823 _____ */
/* 126908 */    0x0000, /* dw 126824 empty */
/* 126909 */    0x0005, /* dw 126825 _____ */
/* 126910 */    0x2041, /* dw 126826 _____ */
/* 126911 */    0x0000, /* dw 126827 empty */
/* 126912 */    0x0000, /* dw 126828 empty */

Yes, the data words 126825 and 126826 are not empty. They must contain the LUT equation.

What about the LUT inputs?

PlanAhead does not show enough details, and you have to fallback to FPGA Editor. One can see the selected input among A0 to A6 in the slice view.