XC6SLX9 die layout and bitstream

The silicium layout of FPGAs is (always?) made of a repetitive pattern, hence the configuration system features a kind of coordinate system, in order to select which tile is being configured.

The Xilinx configuration guide [UG380] and the documentation of the logic blocks [UG384] give some insights about the internal layout of the Spartan6 FPGA, acknowledging that the layout is repetitive, but no exhaustive description is made. Older FPGA in the Xilinx family are better documented, such as the first Virtex in the [XAPP151] application notes.

With information extracted from the source code of FpgaTools [1], here is the internal layout of the Spartan-6 XC6SLX9 silicium die. Independently from the package of the LX9 (TQG144, CPG196, CSG225, FTG256, or CSG324, see [UG385] at p. 16 (v2.3)), the silicium die is always the same and feature 200 I/Os. Some of them are unbounded if the package does not offers enough pins (like the TQG144 that I have).

Meaning of each column (see [UG384], p.8 (v1.1)):

  • M: "Memory" logic slices (31 minors)
  • L: "Arithmetic" logic slices (30 minors)
  • B: BRAM (25 minors)
  • D: DSP (MACC) (24 minors)

Special columns:

  • left: (30 minors)
  • R: center (31 minors)
  • right: (30 minors)

The major and minor information are references to the bitstream sequence.

From bitstream layout to die layout

One Spartan-6 bitstream frame is always 65 16-bit words (130 bytes). The configuration of one CLB (Configurable Logical Block) takes 64 bits (8 bytes, 4 16-bit words) in the bitstream, hence one frame can configure 16 CLB (=1 row).

The internal configuration state machine of the Spartan6 will automatically increment the coordinates of the next frame, in a way to enable the bitstream to be pushed as one binary stream starting from the "zero coordinates": (row=0, major=0, minor=0) at the bottom left of the silicium die.

Above is a detailed description of the configuration bits for the M-type CLB column, which contains a SLICEM and a SLICEX. The L-type CLB column are slightly different in the number of minors and the position of the frames encoding the LUTs equations.

[UG380]Spartan-6 FPGA Configuration User Guide http://www.xilinx.com/support/documentation/user_guides/ug380.pdf
[UG384](1, 2) Spartan-6 FPGA Configurable Logic Block http://www.xilinx.com/support/documentation/user_guides/ug384.pdf
[XAPP151]Virtex Series Configuration Architecture User Guide http://www.xilinx.com/support/documentation/application_notes/xapp151.pdf
[UG385]Spartan-6 FPGA Packaging http://www.xilinx.com/support/documentation/user_guides/ug385.pdf
[1]FpgaTools https://github.com/Wolfgang-Spraul/fpgatools