When creating a design with a registered output, the D Flip-Flop of the final output (just before the FPGA pads) are moved to IOB blocks. See 
Note: Do not try to move the D Flip-Flop to another location in PlanAhead, the tool will behave fine, but will not save anything in the contraint file (.udf)! By checking with FPGA Editor, you will see that the D Flip-Flop will still be placed in the IOB.
The following constraints will prevent this behavior:
#Created by Constraints Editor (xc6slx9-tqg144-2) - 2014/08/05 INST "out_0" IOB = FALSE; INST "out_1" IOB = FALSE; INST "out_2" IOB = FALSE; INST "out_3" IOB = FALSE;
|||Specifying Registers to be Placed in IOBs http://www.xilinx.com/itp/xilinx10/isehelp/pce_p_registers_in_iob.htm|